Semiconductor memory cells have been fabricated with Fowler-Nordheim tunneling for program and erase functions, and which are used as erasable programmable random access memory cells (EPROM), electrically erasable programmable memory cells (EEPROM) and flash memories.
U.S. Pat. No. 5,055,898 issued Oct. 8, 1991 to Beilstein, Jr. et al. entitled DRAM MEMORY CELL HAVING A HORIZONTAL SOI TRANSFER DEVICE DISPOSED OVER A BURIED STORAGE NODE AND FABRICATION METHODS THEREFOR discloses semiconductor memory cell, and methods of fabricating same, that includes a substrate and a plurality of trench capacitors formed at least partially within the substrate and dielectrically isolated therefrom. A silicon-on-insulator (SOI) region includes a silicon layer that overlies an insulator. The silicon layer is differentiated into a plurality of active device regions, each of which is disposed above one of the electrically conductive regions. Each of the active device regions is coupled to an overlying first electrode, or wordline, for forming a gate node of an access transistor to a second electrode, or bitline, for forming a source node of the access transistor, and to the underlying trench capacitor for forming a drain node of the access transistor. The wordline includes a pair of opposed, electrically insulating vertical sidewalls, and the source node and the drain node of each of the access transistors are each comprised of an electrical conductor disposed upon one of the vertical sidewalls. The array of memory cells further includes structure for coupling the active device regions to the substrate to reduce or eliminate a floating substrate effect.
U.S. Pat. No. 4,999,313 issued Mar. 12, 1991 to Arikawa et al. entitled PREPARATION OF A SEMICONDUCTOR ARTICLE USING AN AMORPHOUS SEED TO GROW SINGLE CRYSTAL SEMICONDUCTOR MATERIAL discloses a semiconductor article together with a process for producing the same which article has a plurality of semiconductor single crystal regions comprising a semiconductor single crystal region of one electroconductive type and a semiconductor single crystal region of the opposite electroconductive type on the same insulator substrate. At least the semiconductor single crystal region of one electroconductive type being provided by forming a different material which is sufficiently greater in nucleation density than the material of the insulator substrate and sufficiently fine to the extent that only one single nucleus of the semiconductor material can grow and then permitting the semiconductor material to grow around the single nucleus formed as the center.
U.S. Pat. No. 4,334,347 issued Jun. 15, 1982 to Goldsmith et al. and entitled METHOD OF FORMING AN IMPROVED GATE MEMBER FOR A GATE INJECTED FLOATING GATE MEMORY DEVICE discloses an improved gate injected, floating gate memory device having improved charge retention and endurance characteristics in which the barrier height for the injection of charge (electrons or holes) into the floating gate is reduced. This is accomplished by utilizing a layer of semi-insulating polycrystalline silicon between the control electrode and the insulating layer of the floating gate.
In a publication by Acovic et al. in the IBM Technical Disclosure Bulletin Vol. 34, No. 6 November 1991 pages 238-241 entitled VACUUM-SEALED SILICON-RICH-OXIDE EEPROM CELL an EEPROM cell is described using electron transport in a vacuum between silicon-rich-oxide injectors on the control and the floating gates. Since vacuum is used instead of SiO.sub.2, the endurance and retention of the cell is very high, making it a candidate for a true non-volatile RAM cell. Use of SRO injectors and of vacuum allows the lowering of the programming voltages.